s3c24x0_nand_platform_data Struct Reference

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Detailed Description

Parameters:

	setup	is the TACLS clock count
	access	is the TWRPH0 clock count
	hold	is the TWRPH1 clock count

Note:

A clock count of 0 means always 1 HCLK clock.

Clock count settings depend on the NAND flash requirements and the current HCLK speed Define platform specific data for the NAND controller and its device

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Field Documentation

uint32_t nand_timing

value for the NFCONF register (timing bits only)