board/a9m2440/config.h File Reference

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Detailed Description

Defines
#define	BOARD_SPECIFIC_CLKDIVN   0x05
#define	BOARD_SPECIFIC_MPLL   ((0x6e << 12) + (3 << 4) + 1)
#define	BOARD_SPECIFIC_UPLL   ((0x3c << 12) + (4 << 4) + 2)

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Define Documentation

#define BOARD_SPECIFIC_CLKDIVN   0x05

Define the main clock configuration to be used in register CLKDIVN.

We must limit the frequency of the connected SDRAMs with the clock ratio setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz

#define BOARD_SPECIFIC_MPLL   ((0x6e << 12) + (3 << 4) + 1)

Define the MPLL configuration to be used in register MPLLCON.

We want the MPLL to run at 399.65 MHz

#define BOARD_SPECIFIC_UPLL   ((0x3c << 12) + (4 << 4) + 2)

Define the UPLL configuration to be used in register UPLLCON.

We want the UPLL to run at 47.98 MHz

#define S3C24XX_CLOCK_REFERENCE   16934400

The external clock reference is a 16.9344 MHz crystal.