Defines | |
| #define | BOARD_SPECIFIC_CLKDIVN 0x003 |
| #define | BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1) |
| #define | BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3) |
| #define BOARD_SPECIFIC_CLKDIVN 0x003 |
Define the main clock configuration to be used in register CLKDIVN.
We must limit the frequency of the connected SDRAMs with the clock ratio setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz
| #define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1) |
Define the MPLL configuration to be used in register MPLLCON.
We want the MPLL to run at 202.80MHz
| #define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3) |
Define the UPLL configuration to be used in register UPLLCON.
We want the UPLL to run at 48.0MHz
| #define S3C24XX_CLOCK_REFERENCE 12000000 |
The external clock reference is a 12.0MHz crystal.
Referenced by s3c24xx_dump_clocks(), s3c24xx_get_mpllclk(), and s3c24xx_get_upllclk().
1.5.6